Altera HardCopy Stratix Devices Deliver ASIC Gain Without the Pain
Altera Offers Industry's Only Complete, Risk-Free Solution From Prototype to Production
SAN JOSE, Calif., June 23 /PRNewswire-FirstCall/ -- Altera Corporation today unveiled its HardCopy Stratix(TM) device family, the latest generation of low-cost mask-programmed devices. Harnessing a powerful FPGA front-end, designers today can now directly target a high-volume HardCopy(TM) device at the very beginning of the design process using the new and distinctive design flow now available in Altera's Quartus(R) II version 3.0 design software. HardCopy Stratix devices are the industry's only complete prototype to volume production solution for high-density designs, taking full advantage of the flexibility, features, and time-to-market benefits of Altera's industry-leading Stratix(TM) FPGAs. Offering up to 100 percent performance improvement over the FPGA, HardCopy Stratix devices deliver all the ASIC gain without the pain, minimizing the high-development costs and long design cycles associated with ASICs.
Compared to the original HardCopy APEX(TM) devices, the new HardCopy Stratix devices deliver higher performance, lower power consumption, and a 30 percent cost reduction for equivalent logic functionality. With this announcement, Altera continues to meet the needs of system manufacturers who today are under tremendous pressure to meet both technical and business objectives. Efficient Channel Coding, for example, has successfully integrated HardCopy APEX devices into their high-volume iPSTAR satellite modem, which will be deployed to millions of homes in the Asia Pacific region. Mark Vanderaar, CEO of the company, said, "Altera's HardCopy solution delivered exactly what we had planned: a low-cost realization of our advanced satellite receiver technology. The day we received our HardCopy prototypes, we dropped them into the FPGA sockets on our iPSTAR satellite Internet modem product and they worked perfectly. The HardCopy process has enabled our team to quickly and cost-effectively get to low-cost volume production."
Higher Performance, Lower Power Consumption, and Lower Cost
System manufacturers targeting a HardCopy Stratix design have the option to stay within their original performance targets, or boost performance by an average of 50 percent -- and in some cases, up to 100 percent. Power consumption also decreased up to 40 percent. Altera focused on lowering costs to assist customers in meeting their system cost targets. By targeting further efficiencies in the structure of the logic elements (LEs) and routing of the HardCopy Stratix architecture, additional cost savings of as much as 30 percent for equivalent functionality, versus the original HardCopy APEX devices, were achieved.
"Altera's HardCopy Stratix solution offers significant differentiation from other products, which was a critical factor in our decision to partner with Altera," said Kuldeep Sandhu, co-founder, president and CEO of Maranti Networks. "The HardCopy option allows Maranti to enter the market quickly with Stratix FPGAs and then migrate to HardCopy devices to manage costs. This solution eliminates much of the risk and significantly shortens our development cycles, giving Maranti a competitive edge."
"Many designers today have been on the hunt for an alternative to their traditional ASIC solutions but have been limited by price, performance, and power consumption. Not anymore," said Tim Colleran, vice president of product marketing at Altera. "HardCopy Stratix devices give both ASIC and FPGA designers the unique ability to leverage all the benefits of programmable logic and also reach the price and performance targets they traditionally could only achieve with ASICs."
Seamless Migration
The HardCopy Stratix devices retain the same advanced features as Stratix FPGAs, including hierarchical clock structure, TriMatrix(TM) memory, and optimized embedded digital signal processing (DSP) blocks. Like the Stratix device family, HardCopy Stratix devices support the same wide range of high-speed interfaces -- including SPI-4.2, 10-Gigabit Ethernet (XSBI), and the RapidIO(TM) standard -- as well as a variety of high-speed I/O standards including the LVDS, LVPECL, and HyperTransport(TM) standards. This enables a risk-free, seamless migration.
Unique Comprehensive Design Flow
What makes the HardCopy Stratix design flow unique is the ability to target a HardCopy device at the very beginning of the design process, while taking full advantage of the performance and power improvements associated with Altera's HardCopy Stratix devices. From the very start, designers can verify timing, performance, and power estimates from within the Quartus II version 3.0 design software, based on actual logic placement on the HardCopy Stratix device. All of this capability is available in a $2000 suite of design tools that is already available to tens of thousands of engineers. ASIC designers looking to lower their total cost of ownership and get their product out quicker than ever before, can now design to win with the new Quartus II software.
State of the Art Technology -- Only From Altera
All of Altera's HardCopy devices are based on a universal base-array with the same architecture as their FPGA counterpart. Only the top two metal layers are customized to implement the customer's design. Architectural enhancements in HardCopy devices include shorter path routes, reduced die size, and the removal of silicon overhead associated with FPGA programmability, resulting in a 60 to 70 percent die size reduction compared to the original Stratix FPGA device.
HardCopy Stratix devices are manufactured on the same reliable, state-of-the art 0.13-micron CMOS process as Stratix FPGAs. In partnership with TSMC, the world's largest wafer foundry, Altera continues to be the only FPGA vendor to ship the most advanced, all-layer-copper, 0.13-micron products in volume.
Availability and Pricing
The HardCopy Stratix device family includes five members ranging in density from 25,660 to 79,040 LEs. All devices are available in FineLine BGA(R) packages. Customer designs will be accepted starting in Q3. Pricing is a function of package option, device performance, and volume. Future volume pricing will range from $25 to $120.
About Quartus II 3.0 Software
Altera's easy-to-use Quartus II design software is the most efficient, comprehensive environment available for designing CPLDs, FPGAs, and HardCopy devices. The Quartus II design software includes a suite of advanced system-level design features, access to Altera's extensive intellectual property portfolio, an advanced place-and-route engine including physical synthesis optimization technology, and comprehensive verification solutions. In addition, the latest third-party EDA synthesis and verification flows have been integrated into the Quartus II design software. For more information about the Quartus II design software, visit http://www.altera.com/software. Designers can also download Altera's no-cost Quartus II Web Edition design software at http://www.altera.com/q2webedition.
About Altera
Celebrating its 20th Anniversary this year, Altera Corporation is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com/.
Safe Harbor
This press release contains "forward-looking statements" that are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward-looking statements are generally preceded by words that imply a future state such as "expected" or that imply that a particular future event or events will occur such as "will." Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risk that future performance is dependent on product development schedules, the design performance of software and other tools, as well as the company's and third parties' development technology and manufacture capabilities. Please refer to the company's Securities and Exchange Commission filings, copies of which are available from the company without charge.
NOTE: Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. HyperTransport is a trademark of the HyperTransport Consortium. RapidIO is a trademark of the RapidIO Trade Association. All other product or service names are the property of their respective holder.
CONTACT: Bruce Fienberg of Altera Corporation, +1-408-544-6397, or newsroom@altera.com.
CONTACT: Bruce Fienberg of Altera Corporation, +1-408-544-6397, or
newsroom@altera.com
Web site: http://www.altera.com/
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